`default_nettype none

`define CLK_FREQ 27_000_000
`define THRESHOLD (`CLK_FREQ / 40) // 需要持续25毫秒

module test_debounce_m (
    input rst_w_ni,
    input clk_w_i,
    input key_a_w_ni,
    input key_b_w_ni,

    output led_green_w_no,
    output led_blue_w_no
);
    debounce_m #(
        .MAX_COUNT_CP_I  (`THRESHOLD),
        .INIT_STATUS_CP_I(1)
    ) key_a_debounce_l_i (
        .rst_w_ni(rst_w_ni),
        .clk_w_i(clk_w_i),
        .signal_w_i(key_a_w_ni),

        .stat_w_o(led_green_w_no),
    );
    debounce_m #(
        .MAX_COUNT_CP_I  (`THRESHOLD),
        .INIT_STATUS_CP_I(1)
    ) key_b_debounce_l_i (
        .rst_w_ni(rst_w_ni),
        .clk_w_i(clk_w_i),
        .signal_w_i(key_b_w_ni),

        .stat_w_o(led_blue_w_no)
    );
endmodule
